1. Field of the Invention
The present invention relates to an output buffer providing multiple voltages at an I/O interface. More specifically, the present invention relates to an output buffer for driving an I/O pad at the desired high voltage level along with providing circuitry for tolerating higher voltages.
2. Discussion of the Related Art
Implementation of integrated circuits using lower dimension feature sizes entails the need of scaling the supply voltages to a lower value. In certain applications, interfacing of circuits operating at different voltages is required. The output buffer of an I/O circuit uses a totem pole output for driving the pad. In a totem pole structure, the source of a P-channel device is connected to the supply voltage. Similarly, the source of an N-channel device is connected to the ground with the drain of both transistors connected together. Whenever a device operating at a lower voltage is connected to a node, which is also driven by some other logic operating at a higher voltage, the common node attains the higher voltage level. As a result, the diode formed by the drain of the P-channel transistor and the N-well in which the said P-channel device is formed, becomes forward biased. The P-channel transistor may also turn on. If any of these things happen, the circuit starts dissipating power and the common node clamps at the lower operating voltage.
Several approaches to solve this problem have been tried. One among them was to use an N-channel device instead of a P-channel device in the totem pole and the gate of the N-channel device was driven at a higher voltage level using a level translator to have full-swing voltage at the pad.
U.S. Pat. 5,952,847 is described with the help of FIG. 1. It illustrates a prior art output buffer. The output buffer circuit includes an output totem pole, a level shifter and logic enable block. The gate of the N-channel device in totem pole 12 used to drive the pad at 3.3V is kept at 5V through a level shifter. The oxide of the N-channel device of the totem pole 12, N-channel and P-channel devices of the level shifter 10 are rated for 5V. These transistors are having LDD structure to prevent short channel effect. The structure will prevent any power dissipation when the common node 14 is driven at 5V by any other logic. The output totem pole gets input from logic enable block 8, which is operating at 3.3V. However, the disadvantage of this circuit is that it needs two power supplies to achieve the goal.